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| wavescale video codec ADV212 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2010 analog devices, inc. all rights reserved. features implementation of a jpeg2000-compatible video codec for video and still images through the ADV212 wavescale video compression/decompression engine identical pinout and footprint to the adv202; and support for all the functionality of the adv202 power reduction of at least 30% compared with adv202 jtag/boundary scan support patented spatial ultraefficient recursive filtering (surf) technology for low power, low cost wavelet-based compression support for both 9/7 and 5/3 wa velet transforms with up to 5 levels of transform 9/7 wavelet support for tiles up to 1.048 million samples 5/3 wavelet support for tiles up to 262,144 samples video interface direct support for itu-r bt.656, smpte 125m pal/ntsc, smpte 274m, smpte 293m (525p), and itu-r bt.1358 (625p) or any video format with a maximum input rate of 65 msps for irreversible mode or 40 msps for reversible mode programmable tile/image size with widths of up to 4096 pixels in single-component mode; maximum tile/image height of 4096 pixels ability to combine 2 or more ADV212s to support full-frame smpte 274m hdtv (1080i) or smpte 296m (720p) flexible, asynchronous sram-style host interface support for glueless connection to most 16-/32-bit microcontrollers and asics 2.5 v or 3.3 v input/output and 1.5 v core supply 2 package and speed grade options 12 mm 12 mm, 121-ball csp_bga with a speed grade of 115 mhz 13 mm 13 mm, 144-ball csp_bga with a speed grade of 150 mhz applications networked video and image distribution systems wireless video and image distribution image archival/retrieval digital cctv and surveillance systems digital cinema systems professional video editing and recording digital still cameras digital camcorders general description the ADV212 wavescale? video compression/decompression (codec) is a single-chip jpeg2000 codec targeted for video and high bandwidth image compression applications that can benefit from the enhanced quality and features provided by the jpeg2000 (j2k) iso/iec15444-1 image compression standard. the part implements the computationally intensive operations of the jpeg2000 image compression standard and provides fully compliant code stream generation for most applications. the dedicated video port of the ADV212 provides glueless con- nection to common digital video standards such as itu-r bt.656, smpte 125m, smpte 293m (525p), itu-r bt.1358 (625p), smpte 274m (1080i), and smpte 296m (720p). a variety of other high speed, synchronous pixel and video formats can also be supported by using the programmable framing and validation signals. the ADV212 is an upgrade version of the adv202, which is identical in pinout and footprint. it supports all of the func- tionality of the adv202 and has the following additional options: jtag/boundary scan support and power reduction of at least 30% compared with the adv202.
ADV212 rev. b | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 jpeg2000 feature support .............................................................. 3 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 supply voltages and current ...................................................... 4 input/output specifications ........................................................ 4 clock and reset specifications ................................................ 5 normal host mo de write operation ..................................... 6 normal host mode read operation ...................................... 7 dreq / dack dma mode single f ifo write operation .. 8 dreq / dack dma mode single fifo read operation . 10 external dm a mode fifo write, burst mode .................. 12 external dma mode fifo read, burst mode ................... 13 streaming mode (jdata) fifo read/write ...................... 14 vdata mode timing ............................................................... 15 raw pixel mode timing ............................................................ 17 jtag timing ............................................................................... 18 absolute maximum ratings .......................................................... 19 thermal resistance .................................................................... 19 esd caution ................................................................................ 19 pin configurations and function descriptions ......................... 20 theory of operation ...................................................................... 25 wavel et engine ........................................................................... 25 entropy codecs ....................................................................... 25 embedded processor system .................................................... 25 memo ry system .......................................................................... 25 internal dma engine ................................................................ 25 ADV212 interfaces ......................................................................... 26 video i nterface (vdata bus) .................................................. 26 host interface (hdata bus) ................................................... 26 direct and indirect registers .................................................... 26 control access registers ........................................................... 27 pin configuration and bus sizes/modes ................................ 27 stage register .............................................................................. 27 jdata mode ............................................................................... 27 external dma engine ............................................................... 27 internal registers ............................................................................ 28 direct registers ........................................................................... 28 indirect registers ........................................................................ 29 pll registers .............................................................................. 30 hardware boot modes and power considerations ............... 31 video input formats ...................................................................... 32 applications informat ion .............................................................. 34 encode multichip mode ......................................................... 34 decode multichip master/slave ............................................ 35 digital still camera/camcorder .............................................. 36 encode/decode sdtv video application ............................. 37 32- bit host application ............................................................. 38 hipi (host interface pixel interface) ................................... 39 jdata interface ......................................................................... 40 outline dimensions ....................................................................... 41 ordering guide .......................................................................... 42 revision history 4/10 rev. a to rev. b added wavescale information .................................... throughout changes to features section ............................................................ 1 changes to table 16 ........................................................................ 20 changes to vi deo interface (vdata bus) section, changes to table 17 ............................................................................................ 26 changes to hardware boot modes section ................................ 31 changes to encode multichip mode section .......................... 34 4/08 rev. 0 to rev. a change to table 1, static current parameter ................................. 4 10/06 revision 0: initial version ADV212 rev. b | page 3 of 44 the ad v212 can process images at a rate of 40 msps in reversible mode and at higher rates when used in irreversible mode. the ADV212 contains a dedicated wavelet transform engine, three entropy codec s, an on - board memory system, and an embedded reduced instructi on set computer (risc) processor t hat can provide a complete jpeg 2000 compression/ decompression solution. the wavelet processor supports the 9/7 irreversible wavelet transform and the 5/3 wavelet transform in reversible and irreversible modes. the entropy codec s s upport all features in the jpeg 2000 part 1 specification except maximum shift region of interest (roi). the ADV212 operates on a rectangular array of pixel samples called a tile. a tile can contain a complete image, up to the maximum supported s ize, or some portion of an image. the maximum horizontal tile size supported depends on the wavelet transform selected and the number of samples in the tile. images larger than the ADV212 maximum tile size can be broken into individual tiles and then sent sequentially to the chip while maintaining a single, fully compli ant jpeg 2000 code stream for the entire image. jpeg 2000 feature support the ADV212 supports a broad set of features that are included in part 1 of the jpeg 2000 standard (iso/iec 15444). dep ending on the particular application requirements, the ADV212 can provide varying levels of jpeg 2000 compression support. it can provide raw code block and attribute data output, which allows the host software to have complete control over generation of th e jpeg 2000 code stream and other aspects of the compression process such as bit - rate control. addition ally , the ADV212 can create a complete, fully compliant jpeg2 000 code stream (j2c) and enhanced file formats such as jp2 . functional block dia gram pixel i/f external dma ctrl wavelet engine internal bus and dma engine pixel i/f ec1 ec2 ec3 embedded risc processor system ram rom ADV212 code fifo pixel fifo attr fifo host i/f 06389-001 fi gure 1 . ADV212 rev. b | page 4 of 44 specificat i ons specifications apply to iovdd = 2.5 v or 3.3 v over the operating temperature range, unless otherwise specified. supply voltages and current table 1. parameter mnemonic min typ max unit dc supply voltage, core v dd 1.425 1.5 1.575 v dc supply voltage, input/output iovdd 2.375 2.5 2.625 v iovdd 3.135 3.3 3.465 v input range v in ?0.3 v ddi/o + 0.3 v operating ambient temperature range in free air t ?40 +25 +85 c static current 1 i dd 60 ma dynamic current, core (jclk 2 frequency = 150 mhz) 3 380 440 ma dynamic current, core (jclk 2 frequency = 108 mhz) 280 320 ma dynamic current, core (jclk 2 frequency = 81 mhz) 210 290 ma dynamic current, input/output 40 50 ma 1 no clock or input/output activity. 2 for a definition of j clk, see figure 32 . 3 ADV212 - 150 only. input/output specifications table 2. parameter mnemonic min typ max unit test conditions high level input voltage v ih (3.3 v) 2.2 v v dd = maximum v ih (2.5 v) 1.9 v v dd = maximum low level input voltage v il (3.3 v, 2.5 v) 0.6 v v dd = minimum high level output voltage v oh (3.3 v) 2.4 v v dd = minimum, i oh = ?0.5 ma v oh (2.5 v) 2.0 v v dd = minimum, i oh = ?0.5 ma low level output voltage v ol (3.3 v, 2.5 v) 0.4 v v dd = minimum, i ol = +2 ma high level input current i ih 1.0 a v dd = maximum, v in = v dd low level input current i il 1.0 a v dd = maximum, v in = 0 v high level three - state leakage current i ozh 1.0 a v dd = maximum, v in = v dd low level three - state leakage current i ozl 1.0 a v dd = maximum, v in = 0 v input pin capacitance c i 8 pf output pin cap acitance c o 8 pf ADV212 rev. b | page 5 of 44 clock and reset specifications table 3. parameter mnemonic min typ max unit mclk period t mclk 13.3 100 ns mclk frequency f mclk 10 75.18 mhz mclk width low t mclkl 6 ns m clk width high t mclkh 6 ns vclk period t vclk 13.4 50 ns vclk frequency f vclk 20 74.60 mhz vclk width low t vclkl 5 ns vclk width high t vclkh 5 ns reset width low t reset 5 mclk cycles 1 1 for a definition of mc lk, see figure 32 . mclk vclk t mclk t mclkh t mclkl t vclkh t vclkl t vclk 06389-010 figure 2 . input clock ADV212 rev. b | page 6 of 44 normal host mode write operation table 4. parameter mnemonic min typ max unit we to ack , direct registers and fifo accesses t ack (direct) 5 1.5 jclk + 7.0 1 ns we to ack , indirect registers t ack (indirect) 5 2.5 jclk + 7.0 1 ns data setup t sd 3.0 ns data hold t hd 1.5 ns address setup t sa 2 ns address hold t ha 2 ns cs to we setup t sc 0 ns cs hold t hc 0 ns write inacti ve pulse width (minimum time until next we pulse) t wh 2.5 jclk 1 ns write active pulse width t wl 2.5 jclk 1 ns write cycle time t wcyc 5 jclk 1 ns 1 for a definition of j clk, see figure 32 . addr hdata t sa t sc t hc t wl t ack t hd t sd t wh t wcyc t ha cs we ack valid 06389-012 figure 3 . normal host mode ? write operation ADV212 rev. b | page 7 of 44 normal host mode read operation table 5. parameter mnemonic min typ max unit rd to ack , direct registers and fifo acc esses t ack (direct) 1 5 1.5 jclk + 7.0 2 ns rd to ack , indirect registers t ack (indirect) 1 10.5 jclk 2 15.5 jclk + 7.0 2 ns read access time, direct registers t drd (direct) 5 1.5 jclk + 7.0 2 ns read access time, indirect registers t drd (indirect) 10.5 jclk 2 15.5 jclk + 7.0 2 ns data hold t hzrd 2 8.5 ns cs to rd setup t sc 0 ns address setup t sa 2 ns cs hold t hc 0 ns address hold t ha 2 ns read inactive pulse width t rh 2.5 jclk 2 ns read active pulse width t rl 2.5 jclk 2 ns read cycle time, direct registers t rcyc 5.0 jclk 2 ns 1 timing relationship between ack falling transition and hdata valid is not guaranteed. hdata val id hold time is guaranteed with respect to rd rising transition. a minimum of three jclk cycles is recommended between ack assert and rd deassert. 2 for a definition of jclk , see figure 32 . addr t sa t sc t ha t hc t rl t ack t drd t hzrd t rh t rcyc hdata cs rd ack valid 06389-011 figure 4 . normal host mode ? read operation ADV212 rev. b | page 8 of 44 dreq / dack dma mode single fifo write operation table 6. parameter mnemonic min typ m ax unit dreq pulse width dreq pulse 1 jclk 1 15 jclk 1 ns dack assert to subsequent dreq delay t dreq 2.5 jclk 1 3.5 jclk + 8.5 1 ns we to dack setup t we su 0 ns data to dack deassert setup t su 2 ns data to dack deassert hold t hd 2 ns dack assert pulse width dack lo w 2 jclk 1 ns dack deassert pulse width dack high 2 jclk 1 ns we hold after dack deassert t we hd 0 ns we assert to fsrq dea ssert (fifo full) wfsrq 1.5 jclk 1 2.5 jclk + 7.5 1 ns dack to dreq deassert (dr puls = 0) t dre q rtn 2.5 jclk 1 3.5 jclk + 9.0 1 ns 1 for a definition of jclk, see figure 32 . we dack dreq hdata 3 2 1 0 dreq pulse t dreq dack high dack low t we su t su t hd t we hd 06389-013 figure 5 . single write for dreq / dack dma mode for assign ed dma channel (edmod0/edmod1[ 14: 1] not programmed to a value of 0000) we dack dreq hdata 0 1 2 t dreq rtn dack high dack low t we su t su t hd t we hd 06389-014 figure 6 . single write for dreq / dack dma mode for assigned dma channel (edmod0/edmod1[ 14:11 ] programmed to a value of 0000) ADV212 rev. b | page 9 of 44 wefb dack dreq hdata 0 1 2 dreq pulse t dreq dack high dack low t we su t su t hd t we hd 06389-015 figure 7 . single write cycle for fly - by dma mode ( dreq pulse width is programmable) rd fcs0 hdata 1 2 fifo not full wfsrq fifo full not written to fifo fsrq0 0 t su t hd 06389-021 figure 8 . single write access for dcs dma mode ADV212 rev. b | page 10 of 44 dreq / dack dma mode single fifo read operation table 7. parameter mnemonic min typ max unit dreq pulse width dreq pulse 1 jclk 1 15 jclk 1 ns dack assert to subsequent dreq delay t dreq 2.5 jclk 1 3.5 jclk + 9.0 1 ns rd to dack setup t rd su 0 ns dack to data valid t rd 2.5 11 ns data hold t hd 1.5 ns dack assert pulse width dack lo w 2 jclk 1 ns dack deassert pulse width dack high 2 jclk 1 ns rd hold after dack deassert t rd hd 0 ns rd assert to fsrq deassert (fifo empty) rd fsrq 1.5 jclk 1 2.5 jclk + 9.0 1 ns dack to dreq deassert (dr puls = 0) t dreq rtn 2.5 jclk 1 3.5 jclk + 9.0 1 ns 1 for a definition of jc lk, see figure 32 . rd dack dreq hdata 0 1 2 t rd t hd dreq pulse t dreq t rd su t rd hd dack high dack low 06389-018 figure 9 . single read for dreq / dack dma mode for assign ed dma channel (edmod0/edmod1[ 14:11 ] not programmed to a value of 0000) rd dack dreq hdata 0 1 2 t rd t hd t dreq rtn t rd su t rd hd dack high dack low 06389-019 figure 10 . single read for dreq / dack dma mode for assign ed dma channel (edmod0/edmod1[ 14:11 ] programmed to a value of 0000) ADV212 rev. b | page 11 of 44 rdfb dack dreq 0 1 2 t rd t hd t dreq dreq pulse t rd su t rd hd dack high dack low hdata 06389-020 figure 11 . single read cycle for fly - by dma mode ( dreq pulse width is programmable) rd fsrq0 fcs0 hdata 0 1 rdfsrq fifo not empty fifo empty t hd t rd 06389-090 figure 12 . single read access for dcs dma mode ADV212 rev. b | page 12 of 44 external dma mode fifo write, burst mo de table 8. parameter mnemonic min typ max unit dreq pulse width 1 dreq pulse 1 jclk 2 15 jclk 2 ns we to dreq deassert (dr puls = 0) t dreq rtn 2.5 jclk 2 3.5 jclk + 7.5 2 ns dack to we setup t dack su 0 ns data setup t su 2.5 ns data hold t hd 2 ns we assert pulse width we lo w 1.5 jclk 2 ns we deassert pulse width we high 1.5 jclk 2 ns we deassert to next dreq t dreq wait 2.5 jclk 2 4.5 jclk + 9.0 2 ns we deassert to dack deassert t we_dack 0 ns 1 applies to assigned dma channel , i f edmod0/edmod1[ 14:11 ] is programmed to a nonzer o value. 2 for a definition of jclk , see figure 32 . dreq dack we hdata we high we low t dack su t hd t su 0 1 13 14 15 t dreq wait dreq pulse t we_dack 06389-022 figure 13 . burst write cycle for dreq /dma mode for assign ed dma channel (edmod0/edmod1[14:1] not programmed to a value of 0000) dreq dack we we high we low t dack su t hd t su 0 1 13 14 15 t dreq wait t dreq rtn hdata t we_dack 06389-023 figure 14 . burst write cycle for dreq /dma mode for assign ed dma channel (edmod0/edmod1[ 14:11 ] programmed to a value of 0000) dreq dack wefb hdata we low t dack su t hd t su 0 1 13 14 15 t dreq wait we high t we_dack 06389-024 t dreq rtn figure 15 . burst write cycle for fly - by dma mode ADV212 rev. b | page 13 of 44 external dma mode fifo read, burst mod e table 9. parameter mnemonic m in typ max unit dreq pulse width 1 dreq pulse 1 jclk 2 15 jclk 2 ns rd to dreq deassert (dr puls = 0) t d req rtn 2.5 jclk 2 3.5 jclk + 7.5 2 ns dack to rd setup t dack su 0 ns rd to data valid t rd 2.5 9.7 ns data hold t hd 2.5 ns rd assert pulse width rd lo w 1.5 jclk 2 ns rd deassert pulse width rd high 1.5 jclk 2 ns rd deassert to next dreq t dreq wait 2.5 jclk 2 3.5 jclk + 7.5 2 ns rd deassert to dack deassert t rd_dack 0 ns 1 applies to assigned dma channel if edmod0 or edmod1 <14:11> is programmed to a nonzero value. 2 for a definition of jclk , see figure 32 . dreq dack hdata 0 1 13 14 15 t dack su t dreq wait t dreq pulse t rd t hd t rd_dack rd rd low rd high 06389-025 figure 16 . burst read cycle for dreq / dack dma mode for ass igned dm a channel (emod0/edmod1[14:11 ] not programmed to a value of 0 dreq dack hdata 0 1 13 14 15 t dack su t dreq wait t dreq rtn t rd t hd t rd_dack rd rd low rd high 06389-026 figure 17 . burst read cycle for dreq / dack dma mode for assigned dma ch annel (emod0/edmod1 [ 14:1 1] programm ed to a value of 0000) dreq dack rdfb t dack su t hd t dreq wait hdata 0 1 13 14 15 t rd t dreq rtn t rd_dack 06389-027 figure 18 . burst read cycle for fly - by dma mode ADV212 rev. b | page 14 of 44 streaming mode (jdata) fifo read/write table 10. parameter mnemonic min typ max unit mclk to jdata valid jdata td 1.5 jclk 1 2 .5 jclk + 9.5 1 ns mclk to valid assert/deassert valid td 1.5 jclk 1 2.5 jclk + 8.0 1 ns hold setup to rising mclk hold su 3 ns hold hold from ri sing mclk hold hd 3 ns jdata setup to rising mclk jdata su 3 ns jdata hold from rising mclk jdata hd 3 ns 1 for a defin ition of jclk, see figure 32 . mclk jdata valid hold hold hd hold su valid td jdata su jdata td jdata hd 06389-028 figure 19 . streaming mode timing ? encode mode jdata output mclk jdata valid hold hold hd hold su valid td jdata su jdata hd 06389-029 figure 20 . streaming mode timing ? decode mode jdata input ADV212 rev. b | page 15 of 44 vdata mode timing table 11. parameter mnemonic min typ max unit vclk to vdata valid delay (vdata output) vdata td 12 ns vdata setup to rising vclk (vdata input) vdata su 4 ns vdata hold from rising vclk (vdata input) vdata hd 4 ns hsync setup to rising vclk hsync su 3 ns hsync hold from rising vclk hsync hd 4 ns vclk to hsync valid delay hsync td 12 ns vsync setup to rising vclk vsync su 3 ns vsync hold from rising vclk vsync hd 4 ns vclk to vsync valid delay vsync td 12 ns field setup to rising vclk field su 4 ns field hold from rising vclk field hd 3 ns vclk to field valid field td 12 decode slave data sync delay (hsync low to first 0xff of eav/sa v code) sync delay 8 1 vclk cycles decode slave data sync delay (hsync low to first data for hvf mode) 10 1 vclk cycles 1 the sync delay value varies according to the application. cr y cb y ff eav ff sav cb y cr vclk vdata (in) 00 00 00 00 vdata su vdata hd 06389-091 figure 21 . encode video mode timing ? ccir 656 mode hsync hsync hd hsync su vclk cb y cb y cr y vdata (in) cr y 06389-092 figure 22 . encode video mode timing ? hvf mode (hsync timing) (hsync programmed for negative polarity) vsync vsync su vclk field field su field hd vsync hd 06389-093 figure 23 . encode video mode timing ? hvf mode (vsync and field timing) (vsync and field programmed for negative pola rity) ADV212 rev. b | page 16 of 44 field su vclk vdata (out) hsync (in) 00 00 vsync (in) field (in) y cb eav ff vdata td vsync hd hsync su hsync hd sync delay vsync su 06389-094 figure 24 . decode video mode timing ccir 656 mode, decode slave (hsync, vsync, and field programmed to negative polarity) field su vdata td vsync hd hsync su vsync su vclk y cr y cb y cb hsync (in) vsync (in) vdata (out) field (in) sync delay hsync hd 06389-095 figure 25 . decode video mode timing hvf mode, decode slave (hsync, vsync, and field programmed to negative polarity) vclk cb y cr vdata (out) ff 00 00 sav hsync (out) vsync (out) field (out) cb hsync td vdata td vsync td field td 06389-096 figure 26 . decode video mode timing ccir 656 mode, decode master (hsync, vsync, and field programmed to negative polarity) vclk cb y cr vdata (out) cb y hsync (out) vsync (out) field (out) cr y cb y vdata td vsync td field td 06389-097 figure 27 . decode video mode timing hvf mode, decode master (hsync, vsync, and field programmed to negative polarity) ADV212 rev. b | page 17 of 44 raw pixel mode timin g table 12. parameter mnemonic min typ max unit vclk to pixeldata valid delay (pixeldata output) 1 vdata td 12 ns pixeld ata setup to rising vclk (pixeldata input) vdata su 4 ns pixeldata hold from rising vclk (pixeldata input) vdata hd 4 ns vclk to vrdy valid delay vrdy td 12 ns vfrm setup to rising vclk (vframe input) vfrm su 3 ns vfrm hold from rising vc lk (vframe input) vfrm hd 4 ns vclk to vfrm valid delay (vframe output) vfrm td 12 ns vstrb setup to rising vclk vstrb su 4 ns vstrb hold from rising vclk vstrb hd 3 ns 1 pixeldata is the actual data on the vdata bus; pins and bus width depend on it but timing does not. raw pixel mode?encode vclk pixel 1 pixel 2 pixel 3 vstrb hd vfrm su vfrm hd vrdy td vstrb su vdata hd vdata su vfrm (in) vstrb (in) vrdy (out) pixeldata (in) raw pixel mode?decode vclk pixel 1 pixel 2 pixel 3 vstrb su vstrb hd vfrm td vdata td vrdy td vfrm (out) vstrb (in) vrdy (out) pixeldata (out) 06389-031 figure 28 . raw pixel modes ADV212 rev. b | page 18 of 44 jtag timing table 13. parameter mnemonic min typ max unit tck period tck 134 ns tdi or tms setup time tdi su 4.0 ns tdi or tms hold time tdi hd 4.0 ns tdo hold time tdo hd 0.0 ns tdo valid tdo valid 10.0 ns trs hold time trs hd 4.0 ns trs setup time trs su 4.0 ns trs pulse width low trs lo w 4 tck cycles tdo valid tdo hd tdi su tdi hd trs su trs hd tck tdo tdi tms trs 06389-032 figure 29 . jtag timing ADV212 rev. b | page 19 of 44 absolute maximum rat ings table 14. parameter rating v dd ? supply voltage, core ?0.3 v to +1.65 v iovdd ? supply voltage, input/output ?0.3 v to + 3.63 v storage temperature ( t s ) ?65c to +150c reflow soldering rohs -c ompliant , 121- ball 260c (20 sec to 40 sec ) rohs -c ompliant, 144- ball 260c (20 sec to 40 sec ) stresses above those l isted under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not i mplied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 15 . thermal resistance package type ja jc unit 144- ball ADV212bbcz 22.5 3.8 c/w 121- ball ADV212bbcz 32.8 7.92 c/w esd caution ADV212 rev. b | page 20 of 44 pin configurations and function descript ions a b c d e f g j h k l 10 8 7 6 3 2 1 9 5 4 11 bottom view (not to scale) 06389-035 figure 30.121 - ball pin configuration a b c d e f g j h k l m 12 11 10 8 7 6 3 2 1 9 5 4 bottom view (not to scale) 06389-036 figure 31 . 144 - ball pin configuration table 16 . pin function descriptions 121- ball package 144- ball package pin o. location pin o. location mnemonic pins sed tpe description 119 l9 132 l12 mclk 1 i system input clock. see the pll registers section. 117 l7 131 l11 reset 1 i reset. causes the ADV212 to immediately reset. cs , rd , we , dack0 , dack1 , dreq0 , and dreq1 must be held high when a reset is applied. 37 to 34, 27 to 25, 16, 15, 24, 14 to 12, 2, 6, 5 d4 to d1, c5 to c3, b5, b4, c2, b3 to b1, a2, a6, a5 64, 49 to 51, 37 to 39, 25 to 27, 13 to 15, 2 to 4 f4 , e1 to e3, d1 to d3, c1 to c3, b1 to b3, a2 to a4 hdata [15:0] 16 i/o host data bus. with hdata [23:16], hdata[27:24], and hdata[31:28], these pins make up the 32 - bit wide host data bus. the async host interface is interfaced together with addr[3:0], cs , we , rd , and ack . unused hdata pins should be pulled down via a 10 k ? resistor. 88, 107, 87, 97 h11, k8, h10, j9 108 to 106, 96 j12 to j10, h12 addr [3:0] 4 i address bus for the host interface. 96 j8 95 h11 cs 1 i chip select. this signal is used to qualify addressed read and write access to the ADV212 using the host interface. 95 j7 94 h10 we 1 1 i write enable used with the host interface. rdfb 2 read enable when fly - by dma is enabled. simultaneous assertion of we and dack low activates the hdata bus, even if the dma channels are disabled. 86 h9 84 g12 rd 1 1 i read enable used with the host interface. wefb 3 write enable when fly - by dma is enabled. simultaneous assertion of rd and dack low activates the hdata bus, even if the dma channels are disabled. ADV212 rev. b | page 21 of 44 121- ball package 144- ball package pin no. location pin no. location mnemonic pins used type description 85 h8 83 g11 ack 1 o acknowledge . used for direct register accesses. this signal indicates that the last register access was successful. due to synchronization issues, control a nd status register accesses may incur an additional delay; therefore, the host software should wait for acknowl edgment from the ADV212 before attempting another register access. accesses to the fifos (external dma modes), on the other hand, are guaranteed to occur immediately, provided that space is available; therefore, the host software does not need to wait for ack before attempting another register access, provided that the timing constraints are observed. if ack is shared with more than one device, ack should be connected to a pull - up resist or (10 k ?) and the pll_hi register, bit 4, must be set to 1. 76 g10 82 g10 irq 1 o interrupt. this pin indicates that the ADV212 requires the attention of the host processor. this pin can be programmed to indicate the status of the internal interrupt conditions within the ADV212. the interrupt sources are enabled via the bits in the eirqie register . 63 f8 72 f12 dreq0 1 o data request for external dma interface. indicates that the ADV212 is ready to se nd/receive data to/from the fifo assigned to dma channel 0. fsrq0 o fifo se rvice request. used in dcs - dma m ode. service request from the fifo assigned to channel 0 (asynchronous mode). valid o valid indication for jd ata input/output stream. polarity of this pin is programmable in the edmod0 register. valid is always an output. cfg1 i boot mode configuration. this pin is read on reset to determine the boot configuration of the on - board processor. the pin should be tied to iovdd through a 10 k ? resistor. 64 f9 71 f11 dack0 1 i data acknowledge for external dma interface. signal from the host cpu, which indicates that the data transfer request ( dreq0 ) has been ack nowledged and that the data transfer can proceed. this pin must be held high at all times if the dma interface is not used, even if the dma channels are disabled. hold i external hold indication for jdata input/output stream. polarity is programmable in the edmod0 register. this pin is always an input. fcs0 i fif o chip select. used in dcs - dma m ode. chip select for the fifo assigned to channel 0 (asynchronous mode). ADV212 rev. b | page 22 of 44 121- ball package 144- ball package pin no. location pin no. location mnemonic pins used type description 65 f10 70 f10 dreq1 1 o d ata request for external dma interface. indicates that the ADV212 is ready to send/receive data to/from the fifo assigned to dma channel 1. fsrq1 o fifo se rvice request. used in dcs - dma m ode. service request from the fifo as signed to channel 1 (asynchronous mode). cfg2 i boot mode configuration. this pin is read on reset to determine the boot configuration of the on - board processor. the pin should be tied to dgnd through a 10 k ? resistor. 75 g9 69 f9 dack1 1 i data acknowledge for external dma interface. signal from the host cpu, which indicates that the data transfer request ( dreq1 ) has been ackn owledged and data transfer can proceed. this pin must be held high at all times unless a dma or jdata access is occurring. this pin must be held high at all times if the dma interface is not used, even if the dma channels are disabled. fcs1 i fif o chip select. used in dcs - dma m ode. chip select for the fifo assigned to channel 1 (asynchronous mode). 90 to 92, 78 j2 to j4, h1 111, 97 to 99 k3, j1 to j3 hdata[ 31:28] 4 i/o host expansion bus. jdata[7:4] i/o jdata b us (jdata mode). 79 to 81, 70 h2 to h4, g4 100, 85 to 87 j4, h1 to h3 hdata [27:24] 4 i/o host expansion bus. jd ata [3:0] i/o jdata bus (jdata mode). 69, 68, 59, 58 g3, g2, f4, f3 88, 73 to 75 h4, g1 to g3 hdata [23:20] 4 i/o host expansion b us. 57, 46 to 48 f2, e2, e3, e4 76, 61 to 63 g4, f1 to f3 hdata [19:16] 4 i/o host expansion bus. vdata[15:12] i/o video data. u sed only for raw pixel video mode. unused pins should be pulled down via a 10 k ? resistor. 112 l2 134 m2 scomm7 8 i/o serial communication. f or internal use only. this pin should be tied low via a 10 k ? resistor. 113 l3 135 m3 scomm6 i/o serial communi cation. f or internal use only. this pin should be tied low via a 10 k ? resistor. 114 l4 136 m4 scomm5 i/o serial communication. this pin must be used in multiple chip mode to align the outputs of two or more ADV212s. for details, see the applications information section . when not used, this pin should be tied low via a 10 k ? resistor. 100 k1 121 l1 scomm4 o lcode output in encode mode. when lcode is enabled, the output on this pin indicates on a high transition that th e last data - word for a field has been read from the fifo. for an 8 - bit interface, such as jdata, lcode is asserted for four consecutive bytes and is enabled by default. ADV212 rev. b | page 23 of 44 121- ball package 144- ball package pin no. location pin no. location mnemonic pins used type description 101 k2 122 l2 scomm3 i serial communication. f or internal use only. this pin shou ld be tied low via a 10 k ? resistor. 115 l5 123 l3 scomm2 o serial communication. f or internal use only. this pin should be tied low via a 10 k ? resistor. 103 k4 109 k1 scomm1 i serial communication. f or internal use only. this pin should be tied low via a 10 k ? resistor. 102 k3 110 k2 scomm0 o serial communication. this pin should be tied low via a10 k? resistor. 53 e9 60 e12 vclk 1 i video data clock. this pin must be supplied if video data is input/output on the vdata bus. 44, 43, 29, 31, 32, 18 to 20, 22, 21, 7, 10 d11, d10, c7, c9, c10, b7, b8, b9, b11, b10, a7, a10 46 to 48, 34 to 36, 22 to 24, 9 to 11 d10 to d12, c10 to c12, b10 to b12, a9 to a11 vdata[ 11:0] 12 i/o video data. unused pins should be pulled down via a 10 k ? resisto r. 41 d8 58 e10 vsync 1 i/o vertical sync for video mode. vfrm raw pixel mode framing signal. when this pin is asserted high, it indicates the first sample of a tile. 42 d9 59 e11 hsync 1 i/o horizontal sync for video mode. vrdy o raw pixel mode ready signal. 54 e10 57 e9 field 1 i/o field sync for video mode. vstrb i raw pixel mode transfer strobe. 94 j6 120 k12 tck 1 i jtag clock. if not used, this pin should be connected to ground via a pull - down resisto r. 108 k9 119 k11 trs 1 i jtag reset. if the jtag is used, this pin must be toggled low to high. if jtag is not used, this pin must be held low. 98 j10 118 k10 tms 1 i jtag mode select. if jtag is used, connect a 10 k ? pull - up resistor to this pin. if not used, this pin should be connected to ground via a pull - down resistor. 116 l6 141 m9 tdi 1 i jtag serial data input. if jtag is used, connect a 10 k ? pull - up resistor to this pin. if jtag is not used, this pin should be connected to grou nd via a pull - down resistor. 109 k10 130 l10 tdo 1 o jtag serial data output. if this pin is not used, do not connect it. 3, 8, 40, 84, 120 a3, a8, d7, h7, l10 18, 19, 30, 31, 42, 43, 102, 103, 114, 115, 126, 127, 142 b6, b7, c6, c7, d6, d7, j6, j7, k6, k7, l6, l7, m10 vdd 5/13 v positive supply for core. ADV212 rev. b | page 24 of 44 121- ball package 144- ball package pin no. location pin no. location mnemonic pins used type description 1, 4, 9,11, 23, 33, 39, 45, 49 to 51, 55, 56, 60 to 62, 66, 67, 71 to 73, 77, 83, 89, 99, 110, 111, 118, 121 a1, a4, a9, a11, c1, c11, d6, e1, e5 to e7, e11, f1, f5 to f7, f11, g1, g5 to g7, g11, h6, j1, j11, k11, l1, l8, l11 1, 5 to 8, 12, 17, 20, 29, 32, 41, 44, 52 to 56, 65 to 68, 77 to 81, 89 to 93, 101, 104, 105, 113, 116, 125, 128, 133, 137 to 140, 143, 144 a1, a5 to a8, a12, b5, b8, c5, c8, d5, d8, e4 to e8, f5 to f8, g5 to g9, h5 to h9, j5, j8, j9, k5, k8, l5, l8, m1, m5 to m8, m11, m12 dgnd 29/45 gnd ground. 17, 28, 30, 38, 52, 74, 82, 93, 104 to 106 b6, c6, c8, d5, e8, g8, h5, j5, k5 to k7 16, 21, 28, 33, 40, 45, 112, 117, 124, 129 b4, b9, c4, c9, d4, d9, k4, k9, l4, l9 iovdd 11/10 v positive supply for input/output. 1 in fly - by mode dma, the function s of the rd and we signals (for dma only) are reversed. this allows a host to move data between an external device and the ADV212 with the use of a single strobe. 2 in encode mode with fly - by dma, the host can use the rdfb signal ( we pin) to simultaneously read from the ADV212 and write to an external device such as memory. 3 in decode mode with fly - by dma, the host can use the wefb signal ( rd pin) to simultaneously read from the external device and write to the ADV212. ADV212 rev. b | page 25 of 44 theory of operation the input video or pixel data is passed to the ADV212 pixel interface, and samples are deinterleaved and passed to the wavelet engine, which decomposes each tile or frame into subbands using t he 5/3 or 9/7 filters. the resultant wavelet coefficients are then written to the internal memory. the entropy codec s code the image data so that it conforms to the jpeg 2000 standard. an internal dma provides high bandwidth memory - to - memory transfers, as well as high performance transfers between functional blocks and memory. wavelet engine the ADV212 provides a dedicated wavelet transform processor based on the analog devices , inc., proven and patented surf ? technology. this processor can perform up to s ix wavelet decomposition levels on a tile. in encode mode, the wavelet transform processor takes in uncompressed samples, performs the wavelet transform and quantization, and writes the wavelet coefficients in all frequency subbands to the internal memory. each of these subbands is further broken down into code blocks. the code - block dimensions can be user defined and are used by the wavelet transform processor to organize the wavelet coefficients into code blocks when writing to the internal memory. each c ompleted code block is then entropy coded by one of the entropy codec s. in decode mode, wavelet coefficients are read from internal memory and recomposed into uncompressed samples. entropy codec s the entropy codec block performs context modeling and arit hmetic coding on a code block of the wavelet coefficients. additionally, this block also performs the distortion metric calculations during compression that are required for optimal rate and distortion performance. because the entropy coding process is the most computationally intensive operation in the jpeg 2000 compression process, three dedicated hardware entropy codec s are provided on the ADV212. embedded processor system the ADV212 incorporates an embedded 32 - bit risc processor. this processor is used for configuration, control, and manage - ment of the dedicated hardware functions, as well as for parsing and generat ing the jpeg 2000 code stream. the processor system includes memory for both the program and data memory, the interrupt controller, the standar d bus interfaces, and other hardware functions such as timers and counters. memory system the main function of the memory system is to manage wavelet coefficient data, interim code - block attribute data, and temporary workspace for creating, parsing, and st oring the jpeg 2000 code stream. the memory system can also be used for the program and data memory for the embedded processor. internal dma engine the internal dma engine provides high bandwidth memory - to - memory transfers, as well as high performance trans fers between memory and functional blocks. this function is critical for high speed generation and parsing of the code stream. ADV212 rev. b | page 26 of 44 ADV212 interface s t here are several possible ways to interface to the ADV212 using the vdata bus and the hdata bus or the hd ata bus alone. video interface (vda ta bus) the video interface can be used in applications in which uncompressed pixel data is on a separate bus from compressed data. for example, it is possible to use the vdata bus to input uncompressed video while using the hdata bus to output the compressed data. this interface is ideal for applications requiring very high throughput, such as live video capture. optionally, the ADV212 interlaces itu - r bt.656 resolution video on the fly prior to wavelet processing, which yields significantly better compression performance for temporally coherent frame - based video sources. additionally, high definition digital video such as smpte 274m (1080i) is supported using two or more ADV212 devices. the video interface can support vi deo data or still image data input/output in 8 - /10 - /12 - bit formats, in ycbcr format, or in single input mode. ycbcr data must be in 4:2:2 format. when operating in raw p ixel m ode, only one component can be processed by a single ADV212. video data can be i nput/output in several different modes on the vdata bus, as described in table 17 . in all these modes, the pixel clock must be input on the vclk pin. table 17 . video input/output modes mode description ea v/sav accepts video with embedded eav/sav codes, where the ycbcr data is interleaved onto a single bus. hvf accepts video data accompanied by separate h, v, and f signals, where ycbcr data is interleaved onto a single bus. raw video used for still pi cture data and nonstandard video. vfrm, vstrb, and vrdy are used to program the dimensions of the image. when operating in raw p ixel m ode, only one component can be processed by a single ADV212. host interface (hdat a bus) the ADV212 can connect directly t o a wide variety of host processors and asics using an asynchronous sram - style interface, dma accesses, or streaming mode (jdata) interface. the ADV212 supports 16 - and 32 - bit buses for control and 8- /16 - /32 - bit buses for data transfer. the control and data channel bus widths can be specified independently, which allows the ADV212 to support applica - tions that require control and data buses of different widths. the host interface is used for configuration, control, and status functions, as well as for t ransferring compressed data streams. it can be used for uncompressed data transfers in certain modes. the host interface can be shared by as many as three concurrent data streams in addition to control and status communications. the data streams are ? uncom pressed tile data (for example, still image data) ? fully encoded jpeg 2000 code stream (or unpackaged code blocks) ? code - block attributes the ADV212 uses big endian byte alignment for 16 - and 32 - bit transfers. all data is left - justified (msb). pixel input on the host interface pixel input on the host interface supports 8 - /10 - /12 - /14 - /16 - bit raw pixel data formats. it can be used for pixel (still image) input/output or compressed video output. because there are no timing codes or sync signals associated with th e input data on the host interface, dimension registers and internal counters are used and must be programmed to indicate the start and end of the frame. host bus configuration for maximum flexibility, the host interface provides several configurations to meet particular system requirements. the default bus mode uses the same pins to transfer control, status, and data to and from the ADV212. in this mode, the ADV212 can support 16 - and 32 - bit control transfers and 8 - /16 - /32 - bit data transfers. the size of these buses can be selected independ - ently, allowing, for example, a 16 - bit micro controller to configure and control the ADV212 while still providing 32 - bit data transfers to an asic or external memory system. direct and indirect registers to minimize pin count and cost, the number of address pins is limited to four, which yields a total direct address space of 16 locations. these locations are most commonly used by the external controller and are, therefore, accessible directly. all other registers in t he ADV212 can be accessed indirectly through the iaddr and idata registers. ADV212 rev. b | page 27 of 44 control access regis ters with the exception of the indirect address and data registers (iaddr and idata), all control/status registers in the ADV212 are 16 bits wide and are half - word (16 - bit) addressable only. when 32 - bit host mode is enabled, the upper 16 bits of the hdata bus are ignored on writes and return all zeros on reads of 16 - bit registers. pin configuration an d bus sizes/modes the ADV212 provides a wide variety of contr ol and data configurations, which allows it to be used in many applications with little or no glue logic. the modes described in this section are configured using the busmode register. in this section, host refers to normal addressed accesses ( cs / rd / we /addr) and data refers to external dma accesses ( dreq / dack ). 32- bit host/32 - bit data in this mode, the hdata [ 31:0 ] pins provide full 32 - bit wide data access to the pixel channel , code channel , and attr channel fifos. 16- bit host/32 - bit data this mode allows a 16 - bit host to configure and communicate with the ADV212 while allowing 32 - bit accesses to the pixel, xode , and attr fifos using the external dma capability. all addressed host accesses are 16 bits and, therefore, use only the hdata [ 15:0 ] pins. the hdata [ 31:16 ] pins provide the additional 16 bits necessary to support the 32 - bit external dma transfers to and from the fifos only. 16- bit host/16 - bi t data this mode uses 16 - bit transfers if used for host or external dma data transfers. 16- bit host/8 - bit data (jdata bus mode) this mode provides separate data input/output and host control interface pins. host control accesses are 16 bits and use hdata [ 15:0 ] , whereas the dedicated data bus uses jdata [7:0] . jdata uses a valid/hold synchronous transfer protocol. the direction of the jdata bus is determined by the mode of the ADV212. if the ADV212 is encoding (compression), jdata [ 7:0 ] is an output. if the ADV212 is decoding (decompression), jdata [7:0] is an input. host control accesses remain asynchro - n ous. see also the jdata mode section . stage register because the ADV212 contains both 16 - bit and 32 - bit registers and its internal memory is mapped as 32 - bit data, a mechanism has been provided to allow 16 - bit hosts to access these registers and memory locations using the stage register , which is accessed as a 16 - bit register usin g hdata [15:0]. before writing to the desired register, the stage register must be written with the upper (most significant) half - word. when the host subsequently writes the lower half - word to the desired control register, hdata is combined with the prev - iously staged value to create the required 32 - bit value that is written. when a register is read, the upper (most significant) half - word is returned immediately on hdata , and the lower half - word can be retrieved by reading the stage register on a subsequent access. note that the stage register does not apply to the three data cha nnels (pixel , code , and attr). these channels are always accessed at the specified data width and do not require the use of the stage register. jdata mode jdata mode is typically used only when the dedicated video interface (vdata) is also enabled. this mode allows code stream data (compressed data compliant with jpeg 2000) to be input or output on a single dedicated 8 - bit bus (jdata [7:0]). the bus is always an outpu t during compression operations and an input during decompression. a 2 -p in handshake is used to transfer data over this synchron - ous interface. valid is used to indicate that the ADV212 is ready to provide or accept data and is always an output. hold is always an input and is asserted by the host if it cannot accept/ provide d ata. for example, jdata mode allows real - time appli - cations, in which pixel data is input over the vdata bus while the compressed data stream is output over the jdata bus. external dma engine the external dma interface is provided to enable high bandwidth data input/output between an external dma controller and the ADV212 data fifos. two independent dma channels can each be assigned to any one of the three data stream fifos ( pixel , code , and attr). the controller support s asynchronous dma using a data - reque st/data - acknowledge ( dreq / dack ) protocol in either single or burst access mode. additional functionality is provided for single address compatibility (fly - by) mode and d edicated chip select (dcs) mode . ADV212 rev. b | page 28 of 44 intern al registers this section describes the internal registers of the ADV212. direct registers the ADV212 has 16 direct registers, as listed in table 18 . the direct registers are accessed over the addr[3:0], hdata [31:0], cs , rd , we , and ack pins. the host must first initialize the direct registers before any application - specific operation can be implemented. table 18 . di rect registers address name description 0x00 p ixel pixel fifo access register 0x01 code compressed code stream access register 0x02 at tr attribute fifo access register 0x03 reserved reserved 0x04 cmdsta command stack 0x05 eirqie external interrupt enabled 0x06 eirqflg external interrupt flags 0x07 swflag software flag register 0x08 busmode bus mode configuration register 0x09 mmode miscellaneous mode register 0x0a s tage staging register 0x0b iaddr indirect address registe r 0x0c idata indirect data register 0x0d b oot boot mode register 0x0e pll_hi pll control register, high byte 0x0f pll_lo pll control register, low byte ADV212 rev. b | page 29 of 44 indirect registers in certain modes, such as custom - specific input format or hipi mode, i ndirect registers must be accesse d by the user through the iaddr and idata registers. the indirect register address space starts at internal address 0xffff0000. both 32 - bit and 16 - bit hosts can access the indirect registers: 32- bit hosts use the ia ddr and idata registers, and 16- bit hosts use the iaddr, idata, and stage register s. table 19 . indirect registers address name description 0xffff0400 pmode1 pixel/video format 0xffff0404 comp_cnt_status horizontal count 0xffff0408 line_cnt_status vertical count 0xffff040c xtot total samples per line 0xffff0410 ytot total lines per frame 0xffff0414 f0_start start line of field 0 [f0] 0xffff0418 f1_start start line of field 1 [f1] 0xffff041c v0_start start of activ e video field 0 [f0] 0xffff0420 v1_start start of active video field 1 [f1] 0xffff0424 v0_end end of active video field 0 [f0] 0xffff0428 v1_end end of active video field 1 [f1] 0xffff042c pixel_start horizontal start of active video 0xffff0430 pixel_end horizontal end of active video 0xffff0440 ms_cnt_del master/slave delay 0xffff0444 reserved reserved 0xffff0448 pmode2 pixel mode 2 0xffff044c vmode video mode 0xffff1408 edmod0 external dma mode register 0 0xffff140c edmod1 external dma mode register 1 0xffff1410 ffthrp fifo threshold for pixel fifo 0xffff1414 reserved reserved 0xffff1418 reserved reserved 0xffff141c ffthrc fifo threshold for code fifo 0xffff1420 ffthra fifo threshold for attr fifo 0xffff1424 to 0 xffff14fc reserved reserved ADV212 rev. b | page 30 of 44 pll registers the ADV212 uses the pll_hi and pll_lo direct registers to configure the pll. any time the pll_lo register is modified, the host must wait at least 20 s before reading from or writing to another register. if this delay is not imp lemented, erratic behavior may result. mclk is the input clock to the ADV212 pll and is used to generate the internal jclk (jpeg2000 processor clock) and hclk (embedded cpu clock). the pll can be programmed to have any possible final multiplier value as long as ? jclk > 50 mhz and < 150 mhz (144 - pin version). ? jclk > 50 mhz and < 115 mhz (121 - pin version). ? hclk < 81 mhz (121 - pi n version) or hclk < 108 mhz (144 - pin version). ? jclk 2 vclk for single - component input. ? jclk 2 vclk for ycbcr [4:2:2] input. ? in jdata mode (jdata), jclk must be 4 mclk or higher. ? the maximum burst frequency for external dma modes is 0.36 jclk. ? for mclk frequencies greater than 50 mhz, the i nput clock divider must be enabled; that is, ipd must be set to 1. ipd cannot be enabled for mclk frequencies below 20 mhz. ? deinterlace modes require jclk 4 mclk. ? it is not recommended to use an llc output from a video decoder as a clock source for m clk. to achieve the lowest power consumption, an mclk frequency of 27 mhz is recommended for a standard definition ccir 656 input. the pll circuit is recommended to have a multiplier of 3. this sets jclk and hclk to 81 mhz. lpf phase detect vco jclk hclk 2 hclkd pllmult 2 lfb 2 2 2 ipd bypass mclk 06389-009 figure 32 . pll architecture and control functions table 20 . recommended pll register settings ipd lfb pllmult hclkd hclk jclk 0 0 n 0 n mclk n mclk 0 0 n 1 n mclk/2 n mclk 0 1 n 0 2 n mclk 2 n mclk 0 1 n 1 n mcl k 2 n mclk 1 0 n 0 n mclk/2 n mclk/2 1 0 n 1 n mclk/4 n mclk/2 1 1 n 0 n mclk n mclk 1 1 n 1 n mclk/2 n mclk table 21 . recommended values for pll_hi and pll_lo registers video standard clkin frequency on m clk pll_hi pll_lo smpte 125m or itu - r bt.656 (ntsc or pal) 27 mhz 0x0008 0x0004 smpte 293m (525p) 27 mhz 0x0008 0x0004 itu - r bt.1358 (625p) 27 mhz 0x0008 0x0004 smpte 274m (1080i) 74.25 mhz 0x0008 0x0084 ADV212 rev. b | page 31 of 44 hardware boot modes and power considerations the boot mode can be configured via hardware using the cfg pins or via software. the first boot mode after power - up is set by the cfg pins and should always be as described in the pin listing . cfg1 is tied to iovdd through a 10 k resisto r and cfg2 is ti ed to gnd through a 10 k resistor. there is no special power sequencing requirement for vdd and iovdd. it is strongly recommended that the user place a small decoup - ling cap close to every power pin and at least one bulk cap on each supply. ADV212 rev. b | page 32 of 44 video input formats the ADV212 supports a wide variety of formats for uncom - pressed video and still image data. the actual interface and bus modes selected for transferring uncompressed data dictates the allowed size of the input data and the number of samples transf erred with each access. the host interface can support 8 - /10 - /12 - /14 - /16 - bit data formats. the video interface can support video data or still image data input/output. supported formats are 8 - /10 - /12 - bit ycbcr formats or single component format. all forma ts can support less precision than provided by specifying the actual data width/precision in the pmode register. the maximum allowable data input rate is limited by using irreversible or reversible compression modes and the data width (or precision) of th e inp ut samples. see table 22 and table 24 to determine the maximum data input rate. table 22 . maximum pixel data input rates (144 - ball package) interface compression mode inpu t format input rate limit active resolution (msps) 1 approx imate min imum output rate, compressed data 2 (mbps) approx imate max imum output rate, compressed data 3 ( mbps) hdata irreversible 8- bit data 45 130 200 irreversible 10- bit data 45 130 200 irreversible 12- bit data 45 130 200 irreversible 16- bit data 45 130 200 reversible 8- bit data 40 130 200 reversible 10- bit data 32 130 200 reversible 12- bit data 27 130 200 reversible 14- bit data 23 130 200 vda ta irreversible 8- bit data 65 130 200 irreversible 10- bit data 65 130 200 irreversible 12- bit data 65 130 200 reversible 8- bit data 40 130 200 reversible 10- bit data 32 130 200 reversible 12- bit data 27 130 200 1 input rate limits for hdata may be less for certain applications depending on input picture size and content, host interface settings, and dma transfer s ettings. 2 min imum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate). 3 maximum peak output rate; an output rate above this value is not possible. t able 23 . maximum pixel data input rates (121 - ball package) interface compression mode input format input rate limit active resolution (msps) 1 approx min output rate, compressed data 2 (mbps) approx max output rate, compressed da ta 3 (mbps) hdata irreversible 8- bit data 34 98 150 irreversible 10- bit data 34 98 150 irreversible 12- bit data 34 98 150 irreversible 16- bit data 34 98 150 reversible 8- bit data 30 98 150 reversible 10- bit data 24 98 150 reversible 12- bit data 20 98 150 reversible 14- bit data 17 98 150 vdata irreversible 8- bit data 48 98 150 irreversible 10- bit data 48 98 150 irreversible 12- bit data 48 98 150 reversible 8- bit data 30 98 150 revers ible 10- bit data 24 98 150 reversible 12- bit data 20 98 150 1 input rate limits for hdata may be less for certain applications depending on input picture size and content, host interface settings, and dma transfer settings. 2 min imum guaranteed sustained output rate or minimum sustainable compression rate (input rate/minimum peak output rate). 3 maximum peak output rate; an output rate above this value is not possible. ADV212 rev. b | page 33 of 44 table 24 . maximum supported tile width for data input on hdata and vdata buses compression mode input format tile/precinct maximum width 9/7i single - component 2048 9/7i two - component 1024 each 9/7i three - component 1024 (y) 5/3i single - component 4096 5/3i two - component 2048 (each) 5/3i three - component 2048 (y) 5/3r single - component 4096 5/3r two - component 2048 5/3r three - component 1024 ADV212 rev. b | page 34 of 44 applications information this section describes typical video a pplications for the ADV212 jpeg2000 video processor. encode multichip mode due to the data input rate limitation (see table 22 ), an 1080i application requires at least two ADV212s to encode or decode full - resolution 1080i video. in encode mode, the ADV212 accepts y and cbcr data on separate buses. an encode example is shown in figure 33. in decode mode, a master/slave configuration (as shown in figure 34 ) or a slave/slave configuration can be used to synchronize the outputs of the two ADV212s . applications that have two separate vdata outputs sent to an fpga or buffer before they are sent to an encoder do not require syn chronization at the ADV212 outputs. data[31:0] hdata[31:0] addr[3:0] addr[3:0] cs cs rd rd wr we ack ack irq cs rd wr ack irq dreq dack irq dreq dreq field vsync hsync dack dack gpio scomm[5] vclk 1080i video in mclk vdata[11:2] 32-bit host cpu 10-bit sd/hd video decoder ADV212_1_slave scomm[5] hdata[31:0] addr[3:0] cs rd we ack irq field vsync hsync dreq dack vclk mclk vdata[11:2] ADV212_2_slave llc y[9:0] c[9:0] cbcr cbcr y 74.25mhz osc 06389-002 figure 33 . encode multichip application ADV212 rev. b | page 35 of 44 decode multichip master/sla ve in a master/slave configuration, it is expected that the master hvf outputs are connected to the slave hvf inputs and t hat each scomm 5 pin is connected to the same gpio on the host. in a slave/slave configuration, the common hvf for both ADV212s is generated by an external house sync , and each scomm 5 is connected to the same gpio output on the host. swirq1, software interrupt 1 in the eirqie register, must be unmasked on both devices to enable multichip mode. data[31:0] hdata[31:0] addr[3:0] addr[3:0] cs cs rd rd wr we ack ack irq cs rd wr ack irq dreq dack irq dreq dreq field vsync hsync dack dack gpio scomm[5] vclk 1080i video out mclk vdata[11:2] 32-bit host cpu 10-bit sd/hd video encoder ADV212_1_master scomm[5] hdata[31:0] addr[3:0] cs rd we ack irq field vsync hsync dreq dack vclk mclk v data[11:2] ADV212_2_slave clkin y[9:0] c[9:0] cbcr cbcr y y 74.25mhz osc 06389-003 figure 34 . decode multichip master/slave application ADV212 rev. b | page 36 of 44 digital still camera/camcorder figure 35 is a typical configuration for a digital camera or camcorder. d[9:0] 10 data inputs[9:0] mclk vclk vfrm vrdy vstrb vdata[15:6] pixel out[9:0] sdata serial data sck serial clk sl serial en ad9843a fpga 16-bit host cpu ADV212 data[15:0] hdata[15:0] addr[3:0] addr[3:0] cs cs rd rd we we ack ack irq irq 06389-004 figure 35 . digital still camera/camcorder encode application for 10 - bit pixel data using raw pixel mode ADV212 rev. b | page 37 of 44 encode/decode sdtv v ideo application figure 36 show s two ADV212 chips using a 10 - bit ccir 656 in normal host mode. encode mode 32-bit host cpu ADV212 hdata[31:0] data[31:0] 10-bit video decoder irq intr addr[3:0] addr[3:0] p[19:10] vdata[11:2] video in llc1 mclk 27mhz osc vclk cs cs rd rd we we ack ack 27mhz osc decode mode 32-bit host cpu ADV212 hdata[31:0] data[31:0] 10-bit video encoder irq intr addr[3:0] addr[3:0] p[9:0] vdata[11:2] video out clkin vclk mclk cs cs rd rd we we ack ack 06389-005 figure 36 . encode/decode sdtv video application ADV212 rev. b | page 38 of 44 32-b it host application figure 37 shows two ADV212 chips using a 10 - bit ccir 656 in normal host mode. encode mode 32-bit host cpu ADV212 data[31:0] irq irq addr[3:0] addr[3:0] cs cs rd rd we we ack ack fpga adv7189 10-bit video decoder p[19:10] llc1 v data[11:2] video in vclk mclk dreq0 dreq0 dack0 dack0 hdata[31:0] data[31:0] 27mhz osc 27mhz osc decode mode 31-bit host cpu ADV212 data[31:0] irq irq addr[3:0] addr[3:0] cs cs rd rd we we ack ack fpga 10-bit video encoder p[9:0] vdata[11:2] video out clkin vclk mclk dreq0 dreq0 dack0 dack0 hdata[31:0] data[31:0] 06389-006 figure 37 . encode/decode 32 - bit host application ADV212 rev. b | page 39 of 44 hipi (host interface pixel interface) figure 38 is a typical configuration using h ipi mode. hdata<31> y0/g0 ADV212 rev. b | page 40 of 44 jdata interface figure 39 shows a typical configuration using jdata with a dedicated jdata output, 16 - bit host, and 10 - bit ccir 656. 16-bit host cpu fpga ADV212 hdata[15:0] data[15:0] adv7189 irq irq addr[3:0] addr[3:0] p[19:10] vdata[11:2] field field vs vsync hs llc1 hsync mclk 27mhz osc vclk video in ycrcb cs cs jdata[7:0] hold valid rd rd we we ack ack 06389-008 figure 39 . jdata application ADV212 rev. b | page 41 of 44 outline dimensions *compliant with jedec s t andards mo-192-abd-1 with exception to package height and thickness. detail a 0.70 0.60 0.50 ball diameter 0.20 coplanarity 1.00 bsc 10.00 bsc sq a b c d e f g h j k l 10 8 7 6 3 2 1 9 5 4 11 * 1.31 1.21 1.11 a1 corner index area top view ball a1 corner detail a bottom view 0.50 nom 0.30 min * 1.85 1.71 1.40 12.20 12.00 sq 11.80 082406-a seating plane figure 40 . 121 - ball chip scale package ball grid array [csp_bga] (bc- 121 - 1) dimensions shown in millimeters seating plane detail a 0.70 0.60 0.50 ball diameter coplanarity 0.20 max 1.00 bsc 11.00 bcs sq a b c d e f g j h k l m 12 11 10 8 7 6 3 2 1 9 5 4 0.53 0.43 a1 corner index area top view 13 .00 bsc sq ball a1 indicator detail a bottom view * 1.85 max * 1.32 1.21 1.11 * compliant with jedec standards mo-192-aad-1 with exception to package height and thickness. 021506- a figure 41 . 144 - ball chip scale package ball grid array [csp_bga] (bc- 144 - 3) dimensions shown in millimeters ADV212 rev. b | page 42 of 44 ordering guide model 1 temperature range speed grade operating voltage package description package option ADV212bbcz-115 ?40c to +85c 115 mhz 1.5 v internal, 2.5 v or 3.3 v i/o 121- ball chip scale package ball grid array [csp_bga] bc -121-1 ADV212bbczrl - 115 ?40c to +85c 115 mhz 1.5 v internal, 2.5 v or 3.3 v i/o 121- ball chip scale package ball grid array [csp_bga] bc -121-1 ADV212bbcz-150 ?40c to +85c 150 mhz 1.5 v internal, 2.5 v or 3.3 v i/o 144- ball chip scale package ball grid array [csp_bga] bc -144-3 ADV212bbczrl - 150 ?40c to +85c 150 mhz 1.5 v internal, 2.5 v or 3.3 v i/o 144- ball chip scale package ball gr id array [csp_bga] bc -144-3 1 z = rohs compliant part. ADV212 rev. b | page 43 of 44 notes ADV212 rev. b | page 44 of 44 notes ? 2006 C 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06389 -0- 4/10(b) |
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